From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 15:29:40 +0100
Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
 failure on Fam15h" (fixes a bug that prevent certain RAM modules from
 booting)

This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.

After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
---
 src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index ddaaaab8d5..3b07786b91 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
 		misc2 |= ((cs_mux_67 & 0x1) << 27);
 		misc2 &= ~(0x1 << 26);		/* CsMux45 = cs_mux_45 */
 		misc2 |= ((cs_mux_45 & 0x1) << 26);
+
+		if (pDCTstat->Status & (1 << SB_Registered))
+			misc2 |= 1 << SubMemclkRegDly;
 	} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
 		if (pDCTstat->Status & (1 << SB_Registered)) {
 			misc2 |= 1 << SubMemclkRegDly;
-- 
2.25.1

